FIELD OF THE INVENTION
The invention relates to an integrated memory having 2-transistor/2-capacitor memory cells.
U.S. Pat. No. 5,592,410 discloses an integrated memory of the FRAM (Ferroelectric Random Access Memory) type, which has memory cells of the 2-transistor/2-capacitor type. In that case, each memory cell is formed by two 1-transistor/1-capacitor memory cells disposed at crossover points of word lines and bit lines. In that memory, the 1-transistor/1-capacitor memory cells are disposed at each crossover point between the bit lines and the word lines. The two 1-transistor/1-capacitor memory cells of each 2-transistor/2-capacitor memory cell are connected to two bit lines of a bit line pair in each case. The two bit lines of each bit line pair are disposed adjacent one another.
The memory disclosed in U.S. Pat. No. 5,592,410 has the disadvantage that, given a prescribed dimensioning of the bit lines, of the word lines and also of the spacings between the bit lines and the word lines for the realization of the memory cells (that is to say for their selection transistors and storage capacitors), there is only a certain area available. That is because the structure of the memory cells has to be adapted to the structure prescribed by the word lines and bit lines.